The present invention relates to analog-to-digital converters (ADCs), and more particularly, to gain error calibration in pipelined ADCs.
ADCs convert the amplitude of an analog input voltage signal to a corresponding digital output value for processing by a digital circuit. One of the simplest conventional ADCs is the flash, or direct-conversion, ADC. A flash ADC uses a linear array of comparators to compare the input voltage to a series of reference voltage values—conventionally generated using a voltage ladder—and generate a digital value based on the results of the comparisons. Flash ADCs are among the fastest ADCs. However, increasing the output precision of a flash ADC exponentially increases the number of comparators needed and, consequently, greatly increases the production and usage costs of the flash ADC. As a result, other types of ADCs that are less costly have been developed. One such type of ADC is a pipelined ADC, which is also known as a subranging quantizer.
A pipelined ADC comprises a connected series of stages. The pipelining through the stages allows for a high throughput rate but does generate some data latency. Each stage generates a digital value corresponding to a portion of the digital output value. In addition, each stage, other than the final stage, provides an analog residual signal—representing the difference between (a) the analog signal received by the stage from upstream and (b) an analog signal corresponding to the portion of the digital output value generated by the stage—to the next stage. The digital values generated by the different stages, including the last stage, are processed by a time-alignment and error correction circuit to generate the digital output value representing the original analog input signal applied to the pipelined ADC. The time alignment is performed because each analog sample is processed by a different stage at a different time.
FIG. 1 is a simplified schematic diagram of a conventional pipelined ADC 100, which receives an analog input signal Vin and generates a digital output signal Dout representing the magnitude of the analog input signal Vin. The ADC 100 comprises N stages 101(1)-101(N). Each stage 101, other than the last stage 101(N), operates in substantially the same way.
The first stage 101(1) receives the analog input signal Vin as the input 101a(1) and outputs (a) a first digital value D1 to the summation module 102 via the data path 103a(1) and (b) an analog remainder signal 101b(1) to the second stage 101(2). The first output value D1 represents the one or more most-significant bits of the digital output value Dout. Successive stages output digital values Di representing progressively less-significant bits with the last stage 101(N) outputting an Nth digital value DN representing the one or more least-significant bits. The summation module 102 stores, correlates, and sums the N digital values D1-DN provided by the N stages 101 to provide, via the output path 102a, the digital output value Dout.
In general, the stage 101(i), where i is an integer from 1 to N−1, receives the analog input signal 101a(i), which is provided to the sample-and-hold (S&H) module 104. The S&H module 104 intermittently samples and holds the signal 101a(i) and provides the held output signal 104a to the ADC sub-module 103 and the difference module 105. The ADC sub-module 103 may be a low-resolution flash ADC device, such as, for example, a 3-bit flash ADC. The ADC sub-module 103 outputs the digital output value Di to the summation module 102 and to the DAC sub-module 106 via the data path 103a(i).
The DAC sub-module 106 converts the digital output value Di of the data path 103a into an analog signal for provision as the signal 106a to the difference module 105. The difference module 105 subtracts the analog signal 106a from the held input signal 104a and generates the corresponding remainder signal 105a. The remainder signal 105a is provided to amplifier 107, which multiplies the remainder signal 105a by gain G to generate the residual signal 101b(i), which is provided to the next stage 101(i+1) as the input 101a(i+1) of that next stage 101(i+1). Consequently, the input signal 101a(N), for example, corresponds to the output signal 101b(N−1). The final stage 101(N) does not output a residual signal and does not need any components other than the S&H module 104 and the ADC sub-module 103.
A conventional pipelined ADC may also include calibration circuitry to offset gain errors that may be caused by, for example, capacitor mismatches, limited op-amp gains, and environmental variations. Performing calibration in the background allows for correction that dynamically accounts for variations without interrupting the analog-to-digital conversion.
One conventional calibration method is known as correlation-based background calibration. This method involves adding known random-like noise samples to a stage's remainder signal, which is then amplified by the amplifier in the stage and processed by the following stages (back-end ADC) along with the remainder signal. Random-like samples may be generated by a random-number generator that outputs random or pseudo-random numbers. Since the values of the random-like samples are known, (a) they can be accurately extracted from the ADC's output signal and (b) the effect of gain errors on the samples may be analyzed to determine gain error parameters for the ADC.
FIG. 2 is a simplified schematic diagram of a conventional pipelined ADC 200 that includes background calibration circuitry. Components of the ADC 200 that are similarly labeled but with a different prefix are—unless otherwise indicated—substantially the same as the corresponding elements of the ADC 100 of FIG. 1. Typically, only the first few stages 201 include calibration circuitry. Background calibration is typically performed in reverse order so that if, for example, the stages 201(1)-201(3) include calibration circuitry, then the third stage 201(3) is calibrated first, then the second stage 201(2), and then the first stage 201(1).
Each stage 201 that includes calibration circuitry comprises a random-number (RN) generator 208, a calibration DAC 209, and a difference module 210. Furthermore, the summation and calibration module 202 includes additional circuitry (not shown) for cancelling out the artificial noise signal inserted by the calibration circuitry. The RN generator 208 generates a random-like sequence of digital values whose average (mean) value is zero. These digital values are provided to the calibration DAC 209 via the signal path 208a and converted to analog signals, which are in turn provided to the difference module 210 via the signal path 209a. The difference module 210 subtracts the artificial noise signal 209a from the remainder signal 205a to generate the analog signal 210a, which is in turn provided to the amplifier 207. The amplifier 207 amplifies the analog signal 210a by gain factor G and outputs the residual signal 201b(i) to the next stage 201(i+1). The random-like noise inserted by the RN generator 208 and the DAC 209 is subsequently analyzed by the summation and calibration module 202 to estimate the gain error of the amplifier 207.
Conventional correlation-based background calibration is slow to converge on error-parameter values, sometimes requiring millions of clock cycles to sufficiently converge. Some faster systems utilize additional hardware and still require many thousands of clock cycles to sufficiently converge.